Current mirrors are well known in the art. For example, a conventional P-channel enhancement-mode MOSFET ("PMOS") current mirror 100 is schematically illustrated in FIG. 1. Conventional current mirror 100 includes a V.sub.cc supply voltage terminal 104 and a negative supply voltage terminal 106. V.sub.cc is typically 5 volts and the negative supply voltage is typically 0 volts (i.e. ground).
A first PMOS transistor P1 serves as an input device, having its source connected to V.sub.cc terminal 104 and its drain connected to receive input current I.sub.IN from a current source 102. In practice, current source 102 is likely to be fabricated of additional circuitry contained on the same integrated circuit as current mirror 100. The gate to source voltage of PMOS transistor P1 (abbreviated for clarity as "V.sub.GS(P1) ") varies with the value of the current I.sub.IN forced to flow from the drain of PMOS transistor P1 (i.e. the drain current).
A second PMOS transistor P2 serves as an output device, having its source connected to V.sub.cc terminal 104 and its drain connected to a load L. Since the gate of PMOS transistor P2 is connected to the gate of PMOS transistor P1, the gate to source voltage of PMOS transistor P2 ("V.sub.GS(P2) ") equals V.sub.GS(P1). As a result, if both PMOS transistor P1 and PMOS transistor P2 are operating in the saturation region, the input current I.sub.IN is mirrored through the drain of PMOS transistor P2 as an output current I.sub.OUT. If desired, the sizes of PMOS transistor P1 and PMOS transistor P2 can be ratioed so that I.sub.OUT can be any desired fraction less than or greater than I.sub.IN.
The requirement for PMOS transistor P1 and PMOS transistor P2 operating in the saturation region is now discussed. In general, the relationship between the drain current ("I.sub.D ") and the V.sub.DS of a PMOS transistor defines a family of curves, where each curve exhibits the relationship for a particular V.sub.GS -V.sub.T, V.sub.T being the threshold voltage for the PMOS transistor (i.e. the gate to source voltage at which drain current begins to flow). An example of such a family of curves is shown in FIG. 2. For "small" V.sub.DS 's, the PMOS transistor operates in the linear region, where I.sub.D is approximately proportional to V.sub.DS. For "large" V.sub.DS 's, the PMOS transistor operates in the saturation region, where I.sub.D is approximately constant, regardless of V.sub.DS. The V.sub.DS where the transition is made from the linear region to the saturation region is known as V.sub.DSAT.
Referring again to FIG. 1, it can be seen that the voltage across current source 102 ("V1") varies with the current I.sub.IN drawn by current source 102, since the voltage between V.sub.CC terminal 104 and negative terminal 106 is fixed and V.sub.DS(P1) varies with the current I.sub.IN produced by current source 102. Furthermore, due to the non-negligible impedance of load L, the voltage across load L, and thus V.sub.DS(P2), varies with the current I.sub.OUT from the drain of PMOS transistor P2. But, if both PMOS transistor P1 and PMOS transistor P2 are operated in the saturation region, where I.sub.D depends substantially only on V.sub.GS -V.sub.T, and not on V.sub.DS, since V.sub.GS(P2) is guaranteed to equal V.sub.GS(P1), I.sub.OUT is guaranteed to be related to I.sub.IN only by the ratio of the sizes of PMOS transistor P1 and PMOS transistor P2.
As will now be discussed, due to the configuration in which PMOS transistor P1 is connected in the conventional current mirror circuit 100, PMOS transistor P1 is guaranteed to be always operating in the saturation region. Generally, for a PMOS transistor to be operating in the saturation region, the following condition must be satisfied: EQU V.sub.DS .gtoreq.V.sub.GS -V.sub.T saturation region ( 1a)
Conversely, for a PMOS transistor to be operating in the linear region, the following condition must be satisfied: EQU V.sub.DS &lt;V.sub.GS -V.sub.T linear region ( 1b)
In the current mirror 100, since the drain and gate of PMOS transistor P1 are connected, V.sub.DS(P1) is guaranteed to be always equal to V.sub.GS(P1), and thus the condition in 1(a) is always true for PMOS transistor P1. As a result, PMOS transistor P1 is guaranteed to be always operating in the saturation region.
Furthermore, if the voltage across load L ("V.sub.LOAD ") is kept sufficiently small, then V.sub.DS(P2) (i.e. V.sub.CC -V.sub.LOAD) remains large enough to keep PMOS transistor P2 in the saturation region. V.sub.LOAD is kept small by limiting the impedance of load L (Z.sub.OUT) and/or by limiting the current I.sub.IN being mirrored as I.sub.OUT (remember, V.sub.LOAD =I.sub.OUT *Z.sub.OUT). The voltage V1 on the drain of PMOS transistor P1, which is connected to current source 102, is governed by the following relationship: EQU V1=V.sub.CC -(V.sub.T(P1) +V.sub.DSAT(P1)) (2)
V.sub.T(P1) is typically 1 volt, and V.sub.DSAT(P1) is typically 0.2 to 0.8 volts. Thus, V.sub.T(P1) +V.sub.DSAT(P1) is typically between approximately 1.2 and 1.8 volts, depending on the current flow through PMOS transistor P1, the size of PMOS transistor P1, and the operating temperature of the circuit.
In a typical prior art system wherein V.sub.CC is approximately 5 volts, V1 is within the range of approximately 3.2 to 3.8 volts, which is sufficiently high to allow easy design and fabrication of circuitry within the integrated circuit to serve as input current source 102 and to accommodate various loads L. However, there is an increasing desire to provide integrated circuits capable of operating at lower voltages, for example where V.sub.CC equals 3 volts. In the case, V1 would range from approximately 1.2 volts to 1.8 volts. Given the fact that, in a nominal 3 volt supply, a 10% deviation is acceptable, meaning a legitimate V.sub.CC might be as low as 2.7 bolts, V1 would range from approximately 0.9 to 1.5 volts. This low voltage available as voltage V1 in a conventional current mirror 100 operating at a low V.sub.CC voltage of 2.7 to 3.0 volts is in many circumstances insufficient to allow design and/or proper operation of circuitry serving as current source 102.
FIG. 3 is a schematic illustration of a prior art current mirror 300 that provides improved input voltage headroom. Like the FIG. 1 conventional current mirror 100, current mirror 300 includes V.sub.CC supply voltage terminal 104 and negative supply voltage terminal 106 which is typically connected to ground. Input current I.sub.IN is applied by current source 102 to the drain of PMOS transistor P1, which has its source connected to V.sub.CC terminal 104. The gates of PMOS transistor P1 and P2 are connected in common and the source of PMOS transistor P2 is also connected to V.sub.CC terminal 104. The drain of PMOS transistor P2 is connected to provide output current I.sub.OUT to load L.
As further shown in FIG. 3, N-channel enhancement-mode MOSFET ("NMOS") transistor N11 is a level shift transistor used to provide an increased "headroom" voltage to current source 102. NMOS level shift transistor N11 has its drain connected to V.sub.CC supply terminal 104, its source connected to the commonly connected gates of PMOS transistors P1 and P2, and its gate connected to the drain of PMOS transistor P1 and thus to input current source 102. A bias current source 304 draws bias current I.sub.BIAS through NMOS level shift transistor N11 to ground. Current mirror 300 provides a headroom voltage V1 to current source 102: EQU V1=V.sub.CC -(V.sub.T(P1) +V.sub.DSAT(P1))+V.sub.GS(N11) ( 3)
A further prior art current mirror 400 is shown schematically in FIG. 4. Like the FIG. 3 current mirror 300, current mirror 400 includes V.sub.CC supply voltage terminal 104 and negative supply voltage terminal 106 which is typically connected to ground. Input current I.sub.IN is applied by current source 102 to the drain of PMOS transistor P1, which has its source connected to V.sub.CC terminal 104. The gates of PMOS transistors P1 and P2 are connected in common and the source of PMOS transistor P2 is connected V.sub.CC terminal 104. The drain of PMOS transistor P2 is connected to provide output current I.sub.OUT to load L.
NPN transistor N11' is a bipolar level shift transistor used to provide an increased voltage to current source 102. NPN level shift transistor N11' has its collector connected to V.sub.CC supply terminal 104, its emitter connected to the commonly connected gates of PMOS transistors P1 and P2, and its base connected to the drain of PMOS transistor P1 and thus to input current source 102. A bias current source 304 draws bias current I.sub.BIAS through NPN level shift transistor N11' to ground.
Current mirror 400 provides a voltage V1 to current source 102: EQU V1=V.sub.CC -(V.sub.T(P1) +V.sub.DSAT(P1))+V.sub.be(N11'). (4)
The base to emitter voltage of NPN level shift transistor N11' (V.sub.be(N11') must be kept less than V.sub.T(P1) in order to keep PMOS transistor P1 operating in the saturation region. If V.sub.be(N11') is greater than V.sub.T(P1), PMOS transistor P1 will cease to be saturated and will operate in the linear region, and therefore will not act as current source.
FIG. 5 is a schematic illustration of a yet further prior art current mirror 500. Current mirror 500 includes V.sub.CC supply voltage terminal 154 and negative supply voltage terminal 156 which is typically connected to ground. Input current I.sub.IN is applied by a current source 152 to the drain of NMOS transistor N1, which has its source connected to negative supply voltage terminal 156. The gates of NMOS transistors N1 and N2 are connected in common and the source of MOS transistor N2 is connected to negative supply voltage terminal 156. The drain of NMOS transistor N2 is connected to provide output current I.sub.OUT to load L.
PMOS transistor P11 is a MOS level shift transistor used to provide an increased voltage to current source 152. PMOS level shift transistor P11 has its drain connected to negative voltage supply terminal 156, its source connected to the commonly connected gates of NMOS transistors N1 and N2, and its gate connected to the drain of NMOS transistor N1 and thus to input current source 152. A bias current source 354 draws bias current I.sub.BIAS through PMOS level shift transistor P11 from V.sub.CC voltage supply terminal 154. Current mirror 500 provides a voltage V51 to current source 152: EQU V51=(V.sub.TN1 +V.sub.DSAT(N1))-V.sub.GS(P11) ( 5)
A yet further prior art current mirror 600 is shown schematically in FIG. 6. Current mirror 600 includes V.sub.CC supply voltage terminal 154 and negative supply voltage terminal 156 which is typically connected to ground. Input current I.sub.IN is applied by current source 152 to the drain of NMOS transistor N1, which has its source connected to negative voltage supply terminal 156. The gates of NMOS transistors N1 and N2 are connected in common and the source of NMOS transistor N2 is connected to negative voltage supply terminal 156. The drain of NMOS transistor N2 is connected to provide output current I.sub.OUT to load L.
PNP transistor P11' is a bipolar level shift transistor used to provide an increased voltage to current source 152. PNP level shift transistor P11' has its collector connected to negative voltage supply terminal 156, its emitter connected to the commonly connected gates of NMOS transistors N1 and N2, and its base connected to the drain of NMOS transistor N1 and thus to input current source 152. A bias current source 354 sources bias current I.sub.BIAS through PNP level shift transistor P11' from V.sub.CC.
Current mirror 600 provides a voltage V51 to current source 152: EQU V51=(V.sub.T(N1) +V.sub.DSAT(N1))-V.sub.be(P11'). (6)
The base to emitter voltage of PNP level shift transistor P11' (V.sub.be(P11') must be kept less than V.sub.T(N1) in order to keep NMOS transistor N1 operating in the saturation region. If V.sub.be(P11') is greater than V.sub.T(N1), NMOS transistor N1 will cease to be saturated and will operate in the linear region, and therefore will not act as current source.
A drawback of the current mirrors 300 and 500 is that process variations must be considered in designing for reliable operation. That is, for current mirror 300, if V.sub.T(P1) is low (i.e. fast PMOS) and V.sub.T(N11) (and, therefore, V.sub.GS(N11)) is high (i.e. slow NMOS), current mirror 300 may operate in the linear region rather than the saturation region. Also, operating conditions must be considered since V.sub.T for PMOS devices and V.sub.T for NMOS devices may vary differently with varying temperature. For example, for current mirror 500, if V.sub.T(N1) is low (i.e. fast NMOS) and V.sub.T(P11) (and, therefore, V.sub.GS(P11)) is high (i.e. slow PMOS), current mirror 500 may operate in the linear region rather than the saturation region.
Similarly, for current mirror 400, if V.sub.be(N11') becomes greater than V.sub.T(P1), PMOS transistor P1 will cease to be saturated and will operate in the linear region; and for current mirror 600, if V.sub.be(P11') becomes greater than V.sub.T(N1), NMOS transistor N1 will cease to be saturated and will operate in the linear region. However, since V.sub.T(P1) and Vbe(N11') (and V.sub.T(N1) and V.sub.be(P11')) tend to track nicely over temperature, current mirrors 400 and 600 address the problem of current mirrors 300 and 500 of V.sub.T(P1) and V.sub.T(N1) varying differently with temperature. However, bipolar level shift transistors N11' and P11', respectively, of current mirrors 400 and 600 have a base current error not present in the MOS level shift transistors N11 and P11, respectively, of current mirrors 300 and 500. That is, the bipolar level shift transistor N11' and P11' have a base current such that some of the current I.sub.IN is drawn through the base of the bipolar level shift transistors and therefore not mirrored, causing an error in I.sub.OUT. Futhermore, one of the largest drawbacks of current mirrors 400 and 600 is that emerging process technologies are making it possible to have lower V.sub.T 's, and the such low V.sub.t 's, PMOS transistor P1 of current mirror 400 and NMOS transistor N1 of current mirror 600 still use excess headroom voltage that could be provided to input current source 152 and to load L.